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NXP Semiconductors /LPC176x5x /GPIOINT /CLR2

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Interpret as CLR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P2_0CI)P2_0CI 0 (P2_1CI)P2_1CI 0 (P2_2CI)P2_2CI 0 (P2_3CI)P2_3CI 0 (P2_4CI)P2_4CI 0 (P2_5CI)P2_5CI 0 (P2_6CI)P2_6CI 0 (P2_7CI)P2_7CI 0 (P2_8CI)P2_8CI 0 (P2_9CI)P2_9CI 0 (P2_10CI)P2_10CI 0 (P2_11CI)P2_11CI 0 (P2_12CI)P2_12CI 0 (P2_13CI)P2_13CI 0RESERVED

Description

GPIO Interrupt Clear.

Fields

P2_0CI

Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_1CI

Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_2CI

Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_3CI

Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_4CI

Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_5CI

Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_6CI

Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_7CI

Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_8CI

Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_9CI

Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_10CI

Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_11CI

Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_12CI

Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
P2_13CI

Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
RESERVED

Reserved.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data